The present invention relates to an image signal processor for performing a predetermined signal processing on an image signal output from a solid-state imaging device to generate an image signal complying to a predetermined format.
An imaging apparatus using a solid-state imaging device (CCD image sensor), such as a digital still camera, often uses a battery as a power supply. The range of the output voltage of a battery is limited. Therefore, a regulator or a booster is employed to drive the CCD image sensor.
FIG. 1 is a schematic block diagram of a prior art imaging apparatus 50. The imaging apparatus 50 includes a regulator 2, a CCD image sensor 3, a drive device 4, and an image signal processor 7. The signal processor 7 includes a horizontal driver 8, a signal processing circuit 9, a timing control circuit 13, and an output circuit 14.
The regulator 2 is supplied with power supply voltage from a battery. The regulator 2 converts the power supply voltage to a predetermined voltage Vk. The imaging apparatus 50 is operated with the same operational voltage Vk, which is generated by the imaging device.
The CCD image sensor 3 is, for example, a frame transfer type, and includes an imaging section 3a, a charge section 3b, a horizontal transfer section 3c, and an output section 3d. The imaging section 3a has a plurality of light receiving pixels for storing information charges generated in response to the received light. The charge section 3b temporarily stores the information charges corresponding to a single screen image that is retrieved from the imaging section 3a. The horizontal transfer section 3c sequentially retrieves the information charges from the charge section 3b and sequentially transfers the information charges in the horizontal direction in units of single pixels. The output section 3d receives information charges from the horizontal transfer section 3c, converts the information charges in units of single pixels to voltage values corresponding to the information charges, and generates an image signal Y(t). The image signal Y(t) is provided to the signal processor 7.
The drive device 4 includes a booster 5 and a vertical driver 6, which are formed on the same semiconductor substrate. The booster 5 includes a positive voltage generating charge pump and a negative voltage generating charge pump. The positive voltage generating charge pump increases the regulated voltage VK to a predetermined positive voltage VOH (e.g., 5V) and supplies the positive voltage VOH with the CCD image sensor 3. The negative voltage generating charge pump boosts the voltage to a predetermined negative voltage VOL (e.g., −5V) and supplies the negative voltage VOL with the vertical driver 6.
The vertical driver 6 functions in accordance with the negative voltage VOL and generates a frame transfer clock signal øf and a vertical transfer clock signal øv. The clock signals øf and øv are respectively provided to the imaging section 3a and the charge section 3b of the CCD image sensor 3. The frame transfer clock signal øf and the vertical transfer clock øv are generated in accordance with a frame shift timing signal FT, a vertical synchronizing signal VT, and a horizontal synchronizing signal HT, which are provided from the timing control circuit 13 of the signal processor 7. The information charges that are accumulated in the charge section 3b are line-transferred to the horizontal transfer section 3c at a timing that is in accordance with the vertical synchronizing signal VT and the horizontal synchronizing signal HT.
The horizontal driver 8 functions in accordance with the regulated voltage VK and generates a horizontal transfer clock signal øh. The horizontal transfer clock signal øh is provided to the horizontal transfer section 3c of the CCD image sensor 3. The horizontal transfer clock signal øh is generated in accordance with the vertical synchronizing signal VT and the horizontal synchronizing signal HT, which are provided from the timing control circuit 13 of the signal processor 7. The information charges retrieved in the horizontal transfer section 3c are horizontally transferred at a timing that is in accordance with the horizontal synchronizing signal HT and converted to an image signal Y(t) by the output section 3d. 
The signal processing circuit 9 includes an analog processing circuit 10, an A/D converter 11, and a digital processing circuit 12. The analog processing circuit 10 receives an image signal Y(t) from the CCD image sensor 3 and performs an analog signal processing, such as a correlated double sampling (CDS) process and an automatic gain control (AGC) process, on the image signal Y(t). In the CDS process, the image signal Y(t), which repeats the reset level and the signal level, is clamped at the reset level. Subsequently, the signal level is extracted from the image signal Y(t) and an image signal having a continuous signal level is generated. In the AGC process, the image signals retrieved in the CDS process are integrated in units of single image screens or single vertical scan terms. The gain is feedback-controlled so that the integrated data is included in a predetermined range. The A/D converter 11 receives an image signal from the analog processing circuit 10, standardizes the image signal in synchronism with the image output timing of the CCD image sensor, and generates a digital image data signal Y(n). The digital image data Y(n) is provided to the digital processing circuit 12.
The digital processing circuit 12 performs processes such as color separation and a matrix operation on the digital image signal Y(n) to generate image data Y′ (n), which includes a luminance signal and a chrominance signal. For example, in the color separation process, the digital processing circuit 12 separates the image data Y(n) in accordance with a color array of a color filter, which is attached to the imaging section 3a of the CCD image sensor 3, to generate a plurality of color component signals. In the matrix operation process, the digital processing circuit 12 generates the luminance signal by synthesizing the separated color components and generates the chrominance signal by subtracting luminance components from each color components.
The timing control circuit 13 includes a plurality of counters (not shown), which count a reference clock signal CK that has a constant cycle, and determines a vertical scan and horizontal scan timing of the CCD image sensor 3. The timing control circuit 13 divides the reference clock signal CK, which is provided via a clock supply terminal (not shown), to generate the frame timing signal FT, the vertical synchronizing signal VT, and the horizontal synchronizing signal HT. The timing control circuit 13 provides the analog processing circuit 10, the A/D converter 11, and the digital processing circuit 12 with a timing signal to synchronize the operations of the A/D converter 11 and the digital processing circuit 12 with the operational timing of the CCD image sensor 3.
The output circuit 14 operates with the regulated voltage Vk, receives the image data Y′ (n) from the digital processing circuit 12 of the signal processing circuit 9, and provides the image data Y′ (n) to external device including a central processing unit (CPU) 16, a memory 17, or a display driver 18 via a system bus 15. The CPU 16 centrally controls the operations of the imaging apparatus 50, the memory 17, and the display driver 18 in response to commands from peripheral devices. The memory 17 is a removable memory (e.g., flash memory, a memory card) or a fixed memory (e.g., hard disk), and stores image data Y′ (n), which is provided from the imaging apparatus 50. The display driver 18 receives the image data Y′ (n) from the imaging apparatus 50, drives the display panel 19, and displays a reproduced image.
In the signal processor of the imaging apparatus 50, after the regulator 2 regulates the power supply voltage VDD from the battery to a predetermined regulated voltage Vk, the regulated voltage Vk is commonly supplied to every circuit of the signal processor 7. Thus, the circuits of the signal processor 7 are supplied with the same power supply voltage. The value of the regulated voltage Vk is set in accordance with the operational voltage of the output circuit, which is normally greater than the operation voltage of the signal processing circuit 9. Therefore, even though the signal processing circuit 9 is operated by the power supply voltage, which is less that the regulated voltage Vk, the signal processing circuit 9 is supplied with the regulated voltage Vk, which is greater than the operational voltage. As a result, the signal processing circuit 9 consumes unnecessary power. This may increase the power consumption of the imaging apparatus 50.
In the prior art imaging apparatus 50, to suppress power consumption, the supply of the regulated voltage Vk to the signal processor 7 may be stopped when the signal processor 7 need not be operated. However, due to the following reasons, the level of the voltage supplied to the output circuit must constantly be in accordance with the level of the voltage input to the external device. Therefore, the supply of the power supply voltage cannot easily be stopped. For example, when the signal output from the CCD image sensor 3 is stopped and the external device is operating, current may flow through a system bus 15 from the external device to the output circuit 14 by stopping the supply of the power supply voltage. If the amount of current that flows in this state exceeds the tolerated current amount of the external device or the output circuit 14, the external device or the output circuit 14 may be broken. Accordingly, even if the signal processor 7 stops operating, the signal processor 7 must continuously be supplied with the power supply voltage as long as the external device is operating.